High-performance carry chains for FPGAs

Authors:
Scott Hauck;Matthew M. Hosler;Thomas W. Fry
Affiliations:
Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL;Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL;Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL
Venue:
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Year:
1998

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Abstract

Carry chains are an important consideration for most computations, including FPGAs. Current FPGAs dedicate a portion of their logic to support these demands via a simple ripple carry scheme. In this paper we demonstrate how more advanced carry constructs can be embedded into FPGAs, providing significantly higher performance carry computations. We redesign the standard ripple carry chain to reduce the number of logic levels in each cell. We also develop entirely new carry structures based on high performance adders such as Carry Select, Carry Lookahead, and Brent-Kung. Overall, these optimizations achieve a speedup in carry performance of 3.8 times over current architectures.