High-performance carry chains for FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Efficient Algorithms for Pairing-Based Cryptosystems
CRYPTO '02 Proceedings of the 22nd Annual International Cryptology Conference on Advances in Cryptology
The Montgomery Powering Ladder
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
The Weil Pairing, and Its Efficient Calculation
Journal of Cryptology
Comments on "A Computer Algorithm for Calculating the Product AB Modulo M"
IEEE Transactions on Computers
A Computer Algorithm for Calculating the Product AB Modulo M
IEEE Transactions on Computers
A FPGA Coprocessor for the Cryptographic Tate Pairing over Fp
ITNG '08 Proceedings of the Fifth International Conference on Information Technology: New Generations
An Introduction to Mathematical Cryptography
An Introduction to Mathematical Cryptography
High Speed Compact Elliptic Curve Cryptoprocessor for FPGA Platforms
INDOCRYPT '08 Proceedings of the 9th International Conference on Cryptology in India: Progress in Cryptology
On the Final Exponentiation for Calculating Pairings on Ordinary Elliptic Curves
Pairing '09 Proceedings of the 3rd International Conference Palo Alto on Pairing-Based Cryptography
On Software Parallel Implementation of Cryptographic Pairings
Selected Areas in Cryptography
Faster $\mathbb{F}_p$-Arithmetic for Cryptographic Pairings on Barreto-Naehrig Curves
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Efficient computation of tate pairing in projective coordinate over general characteristic fields
ICISC'04 Proceedings of the 7th international conference on Information Security and Cryptology
Faster squaring in the cyclotomic subgroup of sixth degree extensions
PKC'10 Proceedings of the 13th international conference on Practice and Theory in Public Key Cryptography
Pairing-Friendly elliptic curves of prime order
SAC'05 Proceedings of the 12th international conference on Selected Areas in Cryptography
IEEE Transactions on Information Theory
Implementing cryptographic pairings over barreto-naehrig curves
Pairing'07 Proceedings of the First international conference on Pairing-Based Cryptography
FPGA implementation of pairings using residue number system and lazy reduction
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Security of prime field pairing cryptoprocessor against differential power attack
InfoSecHiComNet'11 Proceedings of the First international conference on Security aspects in information technology
Core based architecture to speed up optimal ate pairing on FPGA platform
Pairing'12 Proceedings of the 5th international conference on Pairing-Based Cryptography
Faster pairing coprocessor architecture
Pairing'12 Proceedings of the 5th international conference on Pairing-Based Cryptography
Secure dual-core cryptoprocessor for pairings over Barreto-Naehrig curves on FPGA platform
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a Pairing Crypto Processor (PCP) over Barreto-Naehrig curves (BN curves). The proposed architecture is specifically designed for field programmable gate array (FPGA) platforms. The design of PCP utilizes the efficient implementation of the underlying finite field primitives. The techniques proposed maximize the utilization of in-built features of an FPGA device which significantly improves the performance of the primitives. Extensive parallelism techniques have been proposed to realize a PCP which requires lesser clock cycles than the existing designs. The proposed design is the first reported result on an FPGA platform for 128-bit security. The PCP provides flexibility to choose the curve parameters for pairing computations. The cryptoprocessor needs 1730 k, 1206 k, and 821 k cycles for the computation of Tate, ate, and R-ate pairings, respectively. On a Virtex-4 FPGA device it consumes 52 kSlices at 50MHz and computes the Tate, ate, and R-ate pairings in 34.6 ms, 24.2 ms, and 16.4 ms, respectively, which is comparable to known CMOS implementations.