High-performance carry chains for FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Identity-Based Encryption from the Weil Pairing
CRYPTO '01 Proceedings of the 21st Annual International Cryptology Conference on Advances in Cryptology
Efficient Algorithms for Pairing-Based Cryptosystems
CRYPTO '02 Proceedings of the 22nd Annual International Cryptology Conference on Advances in Cryptology
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
CRYPTO '96 Proceedings of the 16th Annual International Cryptology Conference on Advances in Cryptology
A One Round Protocol for Tripartite Diffie-Hellman
ANTS-IV Proceedings of the 4th International Symposium on Algorithmic Number Theory
ANTS-V Proceedings of the 5th International Symposium on Algorithmic Number Theory
Using Second-Order Power Analysis to Attack DPA Resistant Software
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
The Montgomery Powering Ladder
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
The Weil Pairing, and Its Efficient Calculation
Journal of Cryptology
Efficient pairing computation on supersingular Abelian varieties
Designs, Codes and Cryptography
A Computer Algorithm for Calculating the Product AB Modulo M
IEEE Transactions on Computers
A FPGA Coprocessor for the Cryptographic Tate Pairing over Fp
ITNG '08 Proceedings of the Fifth International Conference on Information Technology: New Generations
An Introduction to Mathematical Cryptography
An Introduction to Mathematical Cryptography
High Speed Compact Elliptic Curve Cryptoprocessor for FPGA Platforms
INDOCRYPT '08 Proceedings of the 9th International Conference on Cryptology in India: Progress in Cryptology
On the Final Exponentiation for Calculating Pairings on Ordinary Elliptic Curves
Pairing '09 Proceedings of the 3rd International Conference Palo Alto on Pairing-Based Cryptography
Faster $\mathbb{F}_p$-Arithmetic for Cryptographic Pairings on Barreto-Naehrig Curves
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
On compressible pairings and their computation
AFRICACRYPT'08 Proceedings of the Cryptology in Africa 1st international conference on Progress in cryptology
IEEE Transactions on Information Theory
High speed flexible pairing cryptoprocessor on FPGA platform
Pairing'10 Proceedings of the 4th international conference on Pairing-based cryptography
Security of prime field pairing cryptoprocessor against differential power attack
InfoSecHiComNet'11 Proceedings of the First international conference on Security aspects in information technology
Efficient computation of tate pairing in projective coordinate over general characteristic fields
ICISC'04 Proceedings of the 7th international conference on Information Security and Cryptology
Faster squaring in the cyclotomic subgroup of sixth degree extensions
PKC'10 Proceedings of the 13th international conference on Practice and Theory in Public Key Cryptography
Pairing-Friendly elliptic curves of prime order
SAC'05 Proceedings of the 12th international conference on Selected Areas in Cryptography
Efficient Hardware Implementation of Fp-Arithmetic for Pairing-Friendly Curves
IEEE Transactions on Computers
IEEE Transactions on Information Theory
Implementing cryptographic pairings over barreto-naehrig curves
Pairing'07 Proceedings of the First international conference on Pairing-Based Cryptography
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This paper is devoted to the design and the physical security of a parallel dual-core flexible cryptoprocessor for computing pairings over Barreto-Naehrig (BN) curves. The proposed design is specifically optimized for field-programmable gate-array (FPGA) platforms. The design explores the in-built features of an FPGA device for achieving an efficient cryptoprocessor for computing 128-bit secure pairings. The work further pinpoints the vulnerability of those pairing computations against side-channel attacks and demonstrates experimentally that power consumptions of such devices can be used to attack these ciphers. Finally, we suggest a suitable countermeasure to overcome the respective weaknesses. The proposed secure cryptoprocessor needs 1 730 000, 1 206 000, and 821 000 cycles for the computation of Tate, ate, and optimal-ate pairings, respectively. The implementation results on a Virtex-6 FPGA device shows that it consumes 23 k Slices and computes the respective pairings in 11.93, 8.32, and 5.66 ms.