CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
FPGA and ASIC implementations of the ηT pairing in characteristic three
Computers and Electrical Engineering
Compact hardware for computing the tate pairing over 128-bit-security supersingular curves
Pairing'10 Proceedings of the 4th international conference on Pairing-based cryptography
High speed flexible pairing cryptoprocessor on FPGA platform
Pairing'10 Proceedings of the 4th international conference on Pairing-based cryptography
Secure dual-core cryptoprocessor for pairings over Barreto-Naehrig curves on FPGA platform
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Identity based cryptography offers a number of functional advantages over traditional public key cryptosystems and has attracted much research interest in the last few years. The computational costs demanded for such functionalities result to be significantly greater than those bounded to other methods. The overall efficiency of identity based protocols and applications is dominated by the computation of the main used primitive, namely the Tate pairing. The paper focuses on the design of a parallel hardware accelerator for the computation of the Tate pairing that makes use of arithmetics over finite fields with a large prime characteristic. Performance measurements are discussed and compared with previous solutions based on different definitions and algorithms.