A fast algorithm for computing multiplicative inverses in GF(2m) using normal bases
Information and Computation
Reconfigurable Implementation of Elliptic Curve Crypto Algorithms
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Improved Algorithms for Elliptic Curve Arithmetic in GF(2n)
SAC '98 Proceedings of the Selected Areas in Cryptography
Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2)
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A High Performance Reconfigurable Elliptic Curve Processor for GF(2m)
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
An End-to-End Systems Approach to Elliptic Curve Cryptography
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
High Performance FPGA based Elliptic Curve Cryptographic Co-Processor
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
An FPGA implementation of an elliptic curve processor GF(2m)
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
An FPGA Arithmetic Logic Unite for Computing Scalar Multiplication Using the Half-and-Add Method
RECONFIG '05 Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
Cryptographic Algorithms on Reconfigurable Hardware (Signals and Communication Technology)
Cryptographic Algorithms on Reconfigurable Hardware (Signals and Communication Technology)
Parallel Itoh---Tsujii multiplicative inversion algorithm for a special class of trinomials
Designs, Codes and Cryptography
Fast elliptic curve cryptography on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High speed flexible pairing cryptoprocessor on FPGA platform
Pairing'10 Proceedings of the 4th international conference on Pairing-based cryptography
FPGA implementation of binary edwards curve usingternary representation
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Integration, the VLSI Journal
High-Speed unified elliptic curve cryptosystem on FPGAs using binary huff curves
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Pushing the limits of high-speed GF(2m) elliptic curve scalar multiplication on FPGAs
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
Secure dual-core cryptoprocessor for pairings over Barreto-Naehrig curves on FPGA platform
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the implementation of unified arithmetic on binary huff curves
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
| Hi-index | 0.00 |
This paper proposes an efficient high speed implementation of an elliptic curve crypto processor (ECCP) for an FPGA platform. The main optimization goal for the ECCP is efficient implementation of the important underlying finite field primitives namely multiplication and inverse. The techniques proposed maximize the utilization of FPGA resources. Additionally improved scheduling of elliptic curve point arithmetic results in lower number of register files thus reducing the area required and the critical delay of the circuit. Through several comparisons with existing work we demonstrate that the combination of the above techniques helps realize one of the fastest and compact elliptic curve processors.