An FPGA Arithmetic Logic Unite for Computing Scalar Multiplication Using the Half-and-Add Method

Authors:
Sabel Mercurio Hernandez Rodriguez;Francisco Rodriguez-Henriquez
Affiliations:
-;-
Venue:
RECONFIG '05 Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
Year:
2005

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Abstract

In this paper, an FPGA arithmetic logic unit architecture for computing elliptic curve scalar multiplication over the binary extension field GF(2163) is presented. The proposed architecture implements a parallel version of the half-and-add method using the mixed-coordinate representation for point addition, point doubling and point halving primitives. This way, our design can perform elliptic curve point addition, point doubling and point halving efficiently in terms of area resources and timing performance. Our experimental results show that our proposed design can perform an elliptic curve scalar multiplication in about 25µS.