High speed cryptoprocessor for ηT pairing on 128-bit secure supersingular elliptic curves over characteristic two fields

  • Authors:
  • Santosh Ghosh;Dipanwita Roychowdhury;Abhijit Das

  • Affiliations:
  • Computer Science and Engineering, Indian Institute of Technology Khaargpur, WB, India;Computer Science and Engineering, Indian Institute of Technology Khaargpur, WB, India;Computer Science and Engineering, Indian Institute of Technology Khaargpur, WB, India

  • Venue:
  • CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
  • Year:
  • 2011

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Abstract

This paper presents an efficient architecture for computing cryptographic ηT pairing for providing 128-bit security. A cryptoprocessor is proposed for Miller's Algorithm with a new 1223-bit Karatsuba multiplier that exploits parallelism. To the best of our knowledge this is the first hardware implementation of 128-bit secure ηT pairing on supersingular elliptic curves over characteristic two fields. The design has been implemented on Xilinx FPGAs. The place-and-route results show that the proposed design takes only 190µs to complete an 128-bit secure ηT pairing on a Virtex-6 FPGA. The proposed cryptoprocessor achieves eight times speedup compared to the best known existing design. It also outperforms the previous designs with respect to area × time product.