Faster pairing coprocessor architecture

Authors:
Gavin Xiaoxu Yao;Junfeng Fan;Ray C.C. Cheung;Ingrid Verbauwhede
Affiliations:
Department of Electronic Engineering, City University of Hong Kong, Hong Kong SAR;ESAT/SCD-COSIC, KU Leuven, Leuven-Heverlee, Belgium;Department of Electronic Engineering, City University of Hong Kong, Hong Kong SAR;ESAT/SCD-COSIC, KU Leuven, Leuven-Heverlee, Belgium
Venue:
Pairing'12 Proceedings of the 5th international conference on Pairing-Based Cryptography
Year:
2012

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Abstract

In this paper, we present a high-speed pairing coprocessor using Residue Number System (RNS) which is intrinsically suitable for parallel computation. This work improves the design of Cheung et al. [11] using a carefully selected RNS base and an optimized pipeline design of the modular multiplier. As a result, the cycle count for a modular reduction has been halved. When combining with the lazy reduction, Karatsuba-like formulas and optimal pipeline scheduling, a 128-bit optimal ate pairing computation can be completed in less than 100,000 cycles. We prototype the design on a Xilinx Virtex-6 FPGA using 5237 slices and 64 DSPs; a 128-bit pairing is computed in 0.358 ms running at 230MHz. To the best of our knowledge, this implementation outperforms all reported hardware and software designs.