Core based architecture to speed up optimal ate pairing on FPGA platform

Authors:
Santosh Ghosh;Ingrid Verbauwhede;Dipanwita Roychowdhury
Affiliations:
Dept. Electrical Engineering-ESAT/SCD/COSIC, KU Leuven and IBBT, Heverlee-Leuven, Belgium;Dept. Electrical Engineering-ESAT/SCD/COSIC, KU Leuven and IBBT, Heverlee-Leuven, Belgium;Dept. Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur, WB, India
Venue:
Pairing'12 Proceedings of the 5th international conference on Pairing-Based Cryptography
Year:
2012

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Abstract

This paper presents an efficient implementation of optimal-ate pairing over BN curves. It exploits the highly optimized IP cores available in modern FPGAs to speed up pairing computation. The pipelined datapaths for $\mathbb{F}_{p}$-operations and suitable memory cores help to reduce the overall clock cycle count more than 50%. The final design, on a Virtex-6 FPGA, computes an optimal-ate pairing having 126-bit security in 0.375 ms which is a 32% speedup from state of the art result.