A fast algorithm for computing multiplicative inverses in GF(2m) using normal bases
Information and Computation
Novel Radix Finite Field Multiplier for GF(2^m)
Journal of VLSI Signal Processing Systems
Low-Energy Digit-Serial/Parallel Finite Field Multipliers
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
The State of Elliptic Curve Cryptography
Designs, Codes and Cryptography - Special issue on towards a quarter-century of public key cryptography
Efficient Arithmetic on Koblitz Curves
Designs, Codes and Cryptography - Special issue on towards a quarter-century of public key cryptography
Elliptic curves in cryptography
Elliptic curves in cryptography
Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial Basis
IEEE Transactions on Computers
Fast Multiplication on Elliptic Curves over GF(2m) without Precomputation
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
An End-to-End Systems Approach to Elliptic Curve Cryptography
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
New Systolic Architectures for Inversion and Division in GF(2^m)
IEEE Transactions on Computers
Parallel Multipliers Based on Special Irreducible Pentanomials
IEEE Transactions on Computers
High Performance FPGA based Elliptic Curve Cryptographic Co-Processor
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
An FPGA implementation of an elliptic curve processor GF(2m)
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
Customizable elliptic curve cryptosystems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low complexity bit parallel architectures for polynomial basis multiplication over GF(2m)
IEEE Transactions on Computers
High Speed Compact Elliptic Curve Cryptoprocessor for FPGA Platforms
INDOCRYPT '08 Proceedings of the 9th International Conference on Cryptology in India: Progress in Cryptology
FPGA implementation of highly parallelized decoder logic for network coding (abstract only)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Application of data mining in cryptanalysis
ISCIT'09 Proceedings of the 9th international conference on Communications and information technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high-performance unified-field reconfigurable cryptographic processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA implementation of binary edwards curve usingternary representation
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Transactions on computational science XI
Cryptography with asynchronous logic automata
Cryptography and Security
Integration, the VLSI Journal
High-Speed unified elliptic curve cryptosystem on FPGAs using binary huff curves
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Pushing the limits of high-speed GF(2m) elliptic curve scalar multiplication on FPGAs
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and evaluation of random linear network coding Accelerators on FPGAs
ACM Transactions on Embedded Computing Systems (TECS)
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This paper details the design of a new high-speed pipelined application-specific instruction set processor (ASIP) for elliptic curve cryptography (ECC) using field-programmable gate-array (FPGA) technology. Different levels of pipelining were applied to the data path to explore the resulting performances and find an optimal pipeline depth. Three complex instructions were used to reduce the latency by reducing the overall number of instructions, and a new combined algorithm was developed to perform point doubling and point addition using the application specific instructions. An implementation for the United States Government National Institute of Standards and Technology-recommended curve over GF (2163) is shown, which achieves a point multiplication time of 33.05 µs at 91 MHz on a Xilinx Virtex-E FPGA--the fastest figure reported in the literature to date. Using the more modern Xilinx Virtex-4 technology, a point multiplication time of 19.55µs was achieved, which translates to over 51 120 point multiplications per second.