A fast algorithm for computing multiplicative inverses in GF(2m) using normal bases
Information and Computation
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Reconfigurable Implementation of Elliptic Curve Crypto Algorithms
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Fast Multiplication on Elliptic Curves over GF(2m) without Precomputation
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
A High Performance Reconfigurable Elliptic Curve Processor for GF(2m)
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
An End-to-End Systems Approach to Elliptic Curve Cryptography
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
High Performance FPGA based Elliptic Curve Cryptographic Co-Processor
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Fast elliptic curve cryptography on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA implementation of high performance elliptic curve cryptographic processor over GF(2163)
Journal of Systems Architecture: the EUROMICRO Journal
High-Performance Architecture of Elliptic Curve Scalar Multiplication
IEEE Transactions on Computers
High Speed Compact Elliptic Curve Cryptoprocessor for FPGA Platforms
INDOCRYPT '08 Proceedings of the 9th International Conference on Cryptology in India: Progress in Cryptology
On parallelization of high-speed processors for elliptic curve cryptography
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On Repeated Squarings in Binary Fields
Selected Areas in Cryptography
Revisiting the Itoh-Tsujii Inversion Algorithm for FPGA Platforms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Smaller keys for code-based cryptography: QC-MDPC mceliece implementations on embedded devices
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
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In this paper we present an FPGA implementation of a high-speed elliptic curve scalar multiplier for binary finite fields. High speeds are achieved by boosting the operating clock frequency while at the same time reducing the number of clock cycles required to do a scalar multiplication. To increase clock frequency, the design uses optimized implementations of the underlying field primitives and a mathematically analyzed pipeline design. To reduce clock cycles, a new scheduling scheme is presented that allows overlapped processing of scalar bits. The resulting scalar multiplier is the fastest reported implementation for generic curves over binary finite fields. Additionally, the optimized primitives leads to area requirements that is significantly lesser compared to other high-speed implementations. Detailed implementation results are furnished in order to support the claims.