A high performance ECC hardware implementation with instruction-level parallelism over GF(2163)
Microprocessors & Microsystems
Transactions on computational science XI
Pushing the limits of high-speed GF(2m) elliptic curve scalar multiplication on FPGAs
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 14.98 |
A high performance architecture of elliptic curve scalar multiplication based on the Montgomery ladder method over finite field GF(2m) is proposed. A pseudo-pipelined word serial finite field multiplier with word size w, suitable for the scalar multiplication is also developed. Implemented in hardware, this system performs a scalar multiplication in approximately 6⌈m/w⌉(m−1) clock cycles and the gate delay in the critical path is equal to TAND + ⌈log2(w/k)⌉TXOR, where TAND and TXOR are delays due to two-input AND and XOR gates respectively and 1 ≤ k ≪ w is used to shorten the critical path.