A high performance ECC hardware implementation with instruction-level parallelism over GF(2163)

Authors:
Yu Zhang;Dongdong Chen;Younhee Choi;Li Chen;Seok-Bum Ko
Affiliations:
Department of Electrical and Computer Engineering, University of Saskatchewan, 57 Campus Drive, Saskatoon, Canada S7N 5A9 SK;Department of Electrical and Computer Engineering, University of Saskatchewan, 57 Campus Drive, Saskatoon, Canada S7N 5A9 SK;Department of Electrical and Computer Engineering, University of Saskatchewan, 57 Campus Drive, Saskatoon, Canada S7N 5A9 SK;Department of Electrical and Computer Engineering, University of Saskatchewan, 57 Campus Drive, Saskatoon, Canada S7N 5A9 SK;Department of Electrical and Computer Engineering, University of Saskatchewan, 57 Campus Drive, Saskatoon, Canada S7N 5A9 SK
Venue:
Microprocessors & Microsystems
Year:
2010

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Abstract

In this work we propose a high performance elliptic curve cryptographic processor over GF(2^1^6^3) for the applications that require high performance. It has three finite field (FF) RISC cores and a main controller to achieve instruction-level parallelism (ILP) for elliptic curve point multiplication. Customized instructions are proposed to decrease clock cycles. The interconnection among three FF cores and the main controller is obtained based on the analysis of both data dependency and critical path. The proposed design can reach 185MHz with 20,807 slices when implemented on Xilinx XC4VLX80 FPGA device and 263MHz with 217,904 gates when synthesized with TSMC .18@mm CMOS technology.