DAC '96 Proceedings of the 33rd annual Design Automation Conference
Improving functional density through run-time constant propagation
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
A new retiming-based technology mapping algorithm for LUT-based FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
IEEE/ACM Transactions on Networking (TON)
Trading quality for compile time: ultra-fast placement for FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Self Controlling Dynamic Reconfiguration: A Case Study
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
High Speed Homology Search Using Run-Time Reconfiguration
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Assisting Network Intrusion Detection with Reconfigurable Hardware
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Run-Time Reconfigurable System for Gene-Sequence Searching
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Run time reconfiguration of FPGA for scanning genomic databases
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Constant Coefficient Multiplication Using Look-Up Tables
Journal of VLSI Signal Processing Systems
Proceedings of the 41st annual Design Automation Conference
Incremental elaboration for run-time reconfigurable hardware designs
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Reconfigurability-Aware Structural Mapping for LUT-Based FPGAs
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Automatically mapping applications to a self-reconfiguring platform
Proceedings of the Conference on Design, Automation and Test in Europe
TROUTE: a reconfigurability-aware FPGA router
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Robust Boolean reasoning for equivalence checking and functional property verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automating reconfiguration chain generation for SRL-Based run-time reconfiguration
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
An automatic tool flow for the combined implementation of multi-mode circuits
Proceedings of the Conference on Design, Automation and Test in Europe
How to efficiently implement dynamic circuit specialization systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In many applications, subsequent data manipulations differ only in a small set of parameter values. Because of their reconfigurability, FPGAs (field programmable gate arrays) can be configured with a specialized circuit each time the parameter values change. This technique is called dynamic data folding. The specialized circuits are smaller and faster than their generic counterparts. However, the overhead involved in generating the configurations for the specialized circuits at runtime is very large when conventional tools are used, and this overhead will in many cases negate the benefit of using optimized configurations. This article introduces an automatic method for generating runtime parameterizable configurations from arbitrary Boolean circuits. These configurations, in which some of the configuration bits are expressed as a closed-form Boolean expression of a set of parameters, enable very fast run-time specialization, since specialization only involves evaluating these expressions. Our approach is validated on a ternary content-addressable memory (TCAM). We show that the specialized configurations, produced by our method use 2.82 times fewer LUTs than the generic configuration, and even 1.41 times fewer LUTs than the implementation generated by Xilinx Coregen. Moreover, while Coregen needs hand-crafted generators for each type of circuit, our toolflow can be applied to any VHDL design. Using our automatic and generally applicable method, run-time hardware optimization suddenly becomes feasible for a large class of applications.