Hardware speedups in long integer multiplication
ACM SIGARCH Computer Architecture News - Symposium on parallel algorithms and architectures
Improving functional density using run-time circuit reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computing kernels implemented with a wormhole RTR CCM
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Field Programmable Gate Array Based Radar Front-End Digital Signal Processing
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
Microprocessors & Microsystems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
A low-voltage micropower asynchronous multiplier with shift-add multiplication approach
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Layout aware optimization of high speed fixed coefficient FIR filters for FPGAs
International Journal of Reconfigurable Computing
Automatically mapping applications to a self-reconfiguring platform
Proceedings of the Conference on Design, Automation and Test in Europe
Dynamic data folding with parameterizable FPGA configurations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Self-Reconfigurable Constant Multiplier for FPGA
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Design of low-complexity digital finite impulse response filters on FPGAs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Multiplication is an important but expensive operation in most FPGA-based signal processing systems. Many techniques have been introduced for reducing the size and improving the speed of FPGA-based multipliers. Constant-coefficient multipliers are an important class of such multipliers that reduce FPGA resource requirements by exploiting constant-specific optimizations. This paper reviews and analyzes a constant coefficient multiplier that exploits the fine-grain memory resources of FPGAs by performing table look-up. Several optimizations to this multiplier are introduced and analyzed. This paper will also introduce several techniques for reducing the resources of this multiplier by exploiting modern FPGA architectural enhancements.