Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Design of Computers and Other Complex Digital Devices
Design of Computers and Other Complex Digital Devices
An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
FPGA Based Custom Computing Machines for Irregular Problems
HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
Implementation of Multipliers in FPGA Structures
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
FPGA Based Implementation of a Hopfield Neural Network for Solving Constraint Satisfaction Problems
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 2
Constant Coefficient Multiplication Using Look-Up Tables
Journal of VLSI Signal Processing Systems
Image compression by variable block truncation coding with optimalthreshold
IEEE Transactions on Signal Processing
A real-time video signal processing chip
IEEE Transactions on Consumer Electronics
Neural techniques for combinatorial optimization with applications
IEEE Transactions on Neural Networks
An optimal implementation on FPGA of a hopfield neural network
Advances in Artificial Neural Systems
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This paper presents a Field Programmable Gate Array (FPGA) implementation for image/video compression using an improved block truncation coding (BTC) image compression technique. The improvement is achieved by employing a Hopfield neural network (HNN) to calculate a cost function upon which a block is classified as either a high- or a low-detail block. Accordingly, different blocks are coded with different bit rates and thus resulting in better compression ratios. The paper formulates the utilization of HNN within the BTC algorithm in such a way that a viable FPGA implementation is produced. The implementation exploits the inherent parallelism of the BTC/HNN algorithm to provide efficient algorithm-to-architecture mapping. The Xilinx VirtexE BTC implementation has shown to provide a processing speed of about 1.113x10^6 of pixels per second with a compression ratio which varies between 1.25 and 2bits/pixel, according to the image nature.