Computer arithmetic systems: algorithms, architecture and implementation
Computer arithmetic systems: algorithms, architecture and implementation
Improving functional density through run-time constant propagation
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Static and Dynamic Configurable Systems
IEEE Transactions on Computers
Configuration Sequencing with Self Configurable Binary Multipliers
Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing
An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
High Performance Quadrature Digital Mixers for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Dynamic Constant Coefficient Convolvers Implemented in FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Microprocessors & Microsystems
Hi-index | 0.00 |
This paper studies different solutions for carrying out multiplication: a fully functional multiplier denoted as Variable Coefficient Multiplier (VCM), Constant Coefficient Multiplier (KCM) and self-configurable multiplier denoted as Dynamic Constant Coefficient Multiplier (DKCM). For FPGAs which can be easily reconfigured, the choice between the VCM and KCM cannot be easily defined. Furthermore, the DKCM is an additional, middle-way between the KCM and VCM solution, as it offers shorter reprogramming time but occupies more area in comparison with the KCM. In FPGAs, the choice of the optimum multiplier involves three factors: area, propagation and reconfiguration time, which have been thoroughly studied and respective implementation results given. Furthermore, to speed-up implementation of multipliers a design-automated tool has been developed, which generates optimum (for given input parameters), VHDL description of multipliers.