High Performance Quadrature Digital Mixers for FPGAs

Authors:
Francisco Cardells-Tormo;Javier Valls-Coquillat
Affiliations:
-;-
Venue:
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Year:
2002

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Abstract

This paper deals with the optimized implementation of high performance quadrature mixers for transmission. This work examines the most relevant architectures that may be used on FPGAs such as memory compression techniques and the CORDIC algorithm. Each technique is optimized for Virtex FPGAs in terms of area and throughput using relationally placed macros. In order to exploit the high-speed capabilities of these devices we have evaluated several VLSI architectural transforms and arithmetic techniques and we have identified which ones are still successful on FPGAs. We have applied the results of this study to the design of mixers attaining clock rates close to 280MHz.