The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
Spyder: a SURE (SUperscalar and REconfigurable) processor
The Journal of Supercomputing - Special issue on field programmable gate arrays
Digital systems design and prototyping using field programmable logic
Digital systems design and prototyping using field programmable logic
Evolution of Parallel Cellular Machines: The Cellular Programming Approach
Evolution of Parallel Cellular Machines: The Cellular Programming Approach
Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
Reconfigurable Architectures for General-Purpose Computing
Reconfigurable Architectures for General-Purpose Computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A phylogenetic, ontogenetic, and epigenetic view of bio-inspired hardware systems
IEEE Transactions on Evolutionary Computation
Communications of the ACM
Field-programmable gate arrays
Communications of the ACM
A Framework for Run-time Reconfigurable Systems
The Journal of Supercomputing
Adaptive Management of an Active Service Network
BT Technology Journal
Optimization of Run-Time Reconfigurable Embedded Systems
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Dynamic Constant Coefficient Convolvers Implemented in FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Reconfigurable Platform for Academic Purposes
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A non-computationally-intensive neurocontroller for autonomous mobile robot navigation
Biologically inspired robot behavior engineering
Implementation of Multipliers in FPGA Structures
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Journal of VLSI Signal Processing Systems
CODACS Prototype: A Platform-Processor for CHIARA Programs
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 13 - Volume 14
Design of a simulator for mesh-based reconfigurable architectures
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
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Field-programmable gate arrays (FPGAs) are large, fast integrated circuits驴that can be modified, or configured, almost at any point by the end user. Within the domain of configurable computing, we distinguish between two modes of configurability: static驴where the configurable processor's configuration string is loaded once at the outset, after which it does not change during execution of the task at hand, and dynamic驴where the processor's configuration may change at any moment. This paper describes four applications in the domain of configurable computing, considering both static and dynamic systems, including: SPYDER (a reconfigurable processor development system), RENCO (a reconfigurable network computer), Firefly (an evolving machine), and the BioWatch (a self-repairing watch). While static configurability mainly aims at attaining the classical computing goal of improving performance, dynamic configurability might bring about an entirely new breed of hardware devices驴ones that are able to adapt within dynamic environments.