Digital filter synthesis based on minimal signed digit representation
Proceedings of the 38th annual Design Automation Conference
Constant Coefficient Multiplication Using Look-Up Tables
Journal of VLSI Signal Processing Systems
Multiplierless multiple constant multiplication
ACM Transactions on Algorithms (TALG)
Integer and floating-point constant multipliers for FPGAs
ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
Search algorithms for the multiple constant multiplications problem: Exact and approximate
Microprocessors & Microsystems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The multiple constant multiplications (MCM) operation, which realizes the multiplication of a set of constants by a variable, has a significant impact on the complexity and performance of the digital finite impulse response (FIR) filters. Over the years, many high-level algorithms and design methods have been proposed for the efficient implementation of the MCM operation using only addition, subtraction, and shift operations. The main contribution of this paper is the introduction of a high-level synthesis algorithm that optimizes the area of the MCM operation and, consequently, of the FIR filter design, on field programmable gate arrays (FPGAs) by taking into account the implementation cost of each addition and subtraction operation in terms of the number of fundamental building blocks of FPGAs. It is observed from the experimental results that the solutions of the proposed algorithm yield less complex FIR filters on FPGAs with respect to those whose MCM part is implemented using prominent MCM algorithms and design methods.