Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Don't cares in multi-level network optimization
Don't cares in multi-level network optimization
On average power dissipation and random pattern testability of CMOS combinational logic networks
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A survey of optimization techniques targeting low power VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Logic extraction and factorization for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A multiple clocking scheme for low power RTL design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
An estimation technique to guide low power resynthesis algorithms
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Boolean techniques for low power driven re-synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
POSE: power optimization and synthesis environment
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Reducing power dissipation after technology mapping by structural transformations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Multi-level logic optimization for low power using local logic transformations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Logic synthesis using power-sensitive don't care sets
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Gate-level synthesis for low-power using new transformations
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
A gate resizing technique for high reduction in power consumption
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Re-mapping for low power under tight timing constraints
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Technology-dependent transformations for low-power synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Power reduction and power-delay trade-offs using logic transformations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Data driven power optimization of sequential circuits
Proceedings of the conference on Design, automation and test in Europe
Power-efficient ASIC synthesis of cryptographic sboxes
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Low Power VLSI Design Techniques - The Current State
Integrated Computer-Aided Engineering
Efficient evolutionary approaches for the data ordering problem with inversion
EuroGP'06 Proceedings of the 2006 international conference on Applications of Evolutionary Computing
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This paper describes a procedure for minimizing the power consumption in a boolean network under the zero delay model. Power is minimized by modifying the function of each intermediate node in the network such that the power consumption of the node is decreased without increasing the power consumption of the other nodes in the network. A formal analysis of how changes in the switching activity of an intermediate node affect the switching activity of other nodes in the networks is given first. Using this analysis, a procedure for calculating the set of compatible power don't cares for each node in the network is presented. Finally it is shown how these don't cares are used to optimize the network for low power. These techniques have been implemented and results show an average of 10% improvement in total power consumption of the network compared to the results generated by the conventional network optimization techniques.