Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Theory and design of adaptive filters
Theory and design of adaptive filters
The Omega test: a fast and practical integer programming algorithm for dependence analysis
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Numerical recipes in C (2nd ed.): the art of scientific computing
Numerical recipes in C (2nd ed.): the art of scientific computing
Graphics file formats: reference and guide
Graphics file formats: reference and guide
Power-profiler: optimizing ASICs power consumption at the behavioral level
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Activity-sensitive architectural power analysis for the control path
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
High-level synthesis techniques for reducing the activity of functional units
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Scheduling and resource binding for low power
ISSS '95 Proceedings of the 8th international symposium on System synthesis
System level verification of video and image processing specifications
ISSS '95 Proceedings of the 8th international symposium on System synthesis
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
Behavioral Synthesis for low Power
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Energy efficient CMOS microprocessor design
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Decisions taken at the earliest steps of the design of an electronic circuit may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled at algorithmic and architectural level during the design of application-specific integrated circuits (ASICs) in an embedded system scenario. A set of RTL transformations aiming at reducing power consumption are proposed and the potential benefits evaluated. The common idea behind the transformations is to reduce the activity of the data-path functional units (e.g., adders, multipliers) by minimizing the switching activity of their input operands. Functional units contribute highly to the power consumption of the data-path. Preliminary evaluations obtained by simulation show that significant improvements can be achieved. Finally, the paper demonstrates how some of the presented transformations can be automated and incorporated in high-level synthesis tools.