A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Clock skew optimization for ground bounce control
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Clock Skew Optimization for Peak Current Reduction
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Computers and Intractability; A Guide to the Theory of NP-Completeness
Computers and Intractability; A Guide to the Theory of NP-Completeness
Buffer delay change in the presence of power and ground noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Power Distribution Network Design for VLSI
Power Distribution Network Design for VLSI
Buffered Clock Tree for High Quality IC Design
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Minimizing peak current via opposite-phase clock tree
Proceedings of the 42nd annual Design Automation Conference
Fast multi-domain clock skew scheduling for peak current reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Clock buffer polarity assignment for power noise reduction
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Skew aware polarity assignment in clock tree
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A reconfigurable clock polarity assignment flow for clock gated designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This work addresses the problem of minimizing power/ground noise in the clock tree synthesis. Contrary to the previous approaches which only make use of assigning polarities to clock buffers to reduce power/ground noise, our approach solves a new problem of simultaneous consideration of assigning polarities to clock buffers and determining buffer sizes to fully exploit the effects of buffer sizing together with polarity assignment on the minimization of power/ground noise while satisfying the clock skew constraint. Through experiments with MCNC benchmark circuits, it is shown that the proposed solution produces designs with 19.1% less power and 16.2% less ground noise as well as 15.6% less total peak current over that by the conventional method.