A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analysis and Optimization of Power Grids
IEEE Design & Test
Buffer delay change in the presence of power and ground noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Minimizing peak current via opposite-phase clock tree
Proceedings of the 42nd annual Design Automation Conference
Clock buffer polarity assignment for power noise reduction
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Skew aware polarity assignment in clock tree
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization
Proceedings of the 46th Annual Design Automation Conference
Clock tree embedding for 3D ICs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Clock buffer polarity assignment with skew tuning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing
Proceedings of the 48th Design Automation Conference
A reconfigurable clock polarity assignment flow for clock gated designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A new approach to the problem of clock buffer polarity assignment for minimizing power/ground noise on the clock network is presented. The previous approaches solve the assignment problem in two separate steps: (step 1) generating a clock routing tree of minimum total wirelength, satisfying the clock skew constraint and then (step 2) inserting buffering elements with their polarities under the objective of minimizing power/ground noise while satisfying the clock skew constraint. Yet, there is no easy way to predict the result of step 2 during step 1. In our approach, we place the primary importance on the cost of power/ground noise. Consequently, we try to minimize the cost of power/ground noise first and then to construct a clock routing tree later while satisfying the clock skew constraint. Through experimentation using several benchmark circuits, it is shown that this approach is quite effective and produces very good solutions, reducing the power/ground noise by 75% and the peak current by 26% at the expense of 5% wirelength overhead compared to that produced by the conventional approach.