Approximation of Pareto optima in multiple-objective, shortest-path problems
Operations Research
Simultaneous switching noise in on-chip CMOS power distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Buffer delay change in the presence of power and ground noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Minimizing peak current via opposite-phase clock tree
Proceedings of the 42nd annual Design Automation Conference
Multicriteria Optimization
Clock buffer polarity assignment for power noise reduction
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Skew-aware polarity assignment in clock tree
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
International Journal of Applied Mathematics and Computer Science
Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The clock buffer polarity assignment is one of the effective design schemes to mitigate the power/ground noise caused by the clock signal propagation. This work overcomes two fundamental limitations of the conventional clock buffer polarity assignment methods, which are (1) the unawareness of the signal delay (i.e., arrival time) differences to the leaf buffering elements and (2) the ignorance of the effect of the current fluctuation of non-leaf buffering elements on the total peak current waveform. Clearly, not addressing (1) and (2) in polarity assignment may cause a severe inaccuracy on the peak current estimation, which results in unnecessarily high peak current. To overcome the limitations, we propose a completely new fine-grained approach to the clock buffer polarity assignment combined with buffer sizing, formulating the problem into a multi-objective shortest path problem and solving it effectively. The experimental results show that the proposed method is able to produce designs with 17% lower peak current and 20% lower power noise on average compared the results produced by the best ever known method.