Register File Energy Reduction by Operand Data Reuse
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Power-aware clock tree planning
Proceedings of the 2004 international symposium on Physical design
A 500-MHz low-power five-port CMOS register file
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Bypass aware instruction scheduling for register file power reduction
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Opposite-Phase Clock Tree for Peak Current Reduction
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Proceedings of the 6th ACM conference on Computing frontiers
Compiler-assisted power optimization for clustered VLIW architectures
Parallel Computing
Scheduling for register file energy minimization in explicit datapath architectures
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This article discusses the low-power features of Motorola's M*CORE architecture, the first processor designed specifically for sophisticated, yet low-power, applications. A dual-processor solution for a TDMA baseband transceiver, currently in production, is also described. The key features of the 1.8-volt DSP56652 cellular baseband processor, currently designed into the iDEN i1000 phone, highlights the integration of smart peripherals to reduce overall power consumption.