Register File Energy Reduction by Operand Data Reuse

Authors:
Hiroshi Takamura;Koji Inoue;Vasily G. Moshnyaga
Affiliations:
-;-;-
Venue:
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Year:
2002

Citing 7
Cited 1

Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors

MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Designing the TFP Microprocessor

IEEE Micro
Dynamic instruction reuse

Proceedings of the 24th annual international symposium on Computer architecture
Computer architecture (2nd ed.): a quantitative approach

Computer architecture (2nd ed.): a quantitative approach
Power reduction through work reuse

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Micro-RISC Architecture for the Wireless Market

IEEE Micro
Energy-Efficient Register Access

SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design

Leakage Energy Reduction in Register Renaming

ICDCSW '04 Proceedings of the 24th International Conference on Distributed Computing Systems Workshops - W7: EC (ICDCSW'04) - Volume 7

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents an experimental study of register file utilization in conventional RISC-type data path architecture to determine benefits that we can expect to achieve by eliminating unnecessary register file reads and writes. Our analysis shows that operand bypassing, enhanced for operand-reuse can discard the register file accesses up to 65% as a peak and by 39% on average for tested benchmark programs.