A low power SRAM using auto-backgate-controlled MT-CMOS
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Implementation of precise interrupts in pipelined processors
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Measuring Experimental Error in Microprocessor Simulation
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Power-Driven Challenges in Nanometer Design
IEEE Design & Test
The MIPS R10000 Superscalar Microprocessor
IEEE Micro
Register File Energy Reduction by Operand Data Reuse
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Reducing register ports for higher speed and lower energy
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Energy-Efficient Register Access
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
The Alpha 21264 Microprocessor Architecture
ICCD '98 Proceedings of the International Conference on Computer Design
Static energy reduction techniques for microprocessor caches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems
Checkpoint allocation and release
ACM Transactions on Architecture and Code Optimization (TACO)
An adaptive technique for reducing leakage and dynamic power in register files and reorder buffers
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Register files are becoming a power-hungry component in future embedded microprocessors, as a lot of power reduction techniques are applied, especially on caches, which are currently the most power-hungry component. As higher performance is required for coming smart embedded systems, out-of-order execution, which requires a large number of registers, will be adopted in embedded processors. In addition, deep submicron semiconductor technology leads to larger leakage current. All these situations combine to increase leakage energy consumed by registers in embedded processors. In this paper, we propose a solution for this problem. By exploiting the characteristics of register renaming and the benfit from CMOS circuit techniques with sleep mode, we achieve leakage energy reduction of up to 53.6%.