An adaptive technique for reducing leakage and dynamic power in register files and reorder buffers

Authors:
Shadi T. Khasawneh;Kanad Ghose
Affiliations:
Department of Computer Science, State University of New York, Binghamton, NY;Department of Computer Science, State University of New York, Binghamton, NY
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

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Abstract

Contemporary superscalar processors, designed with a one-size-fits-all philosophy, grossly overcommit significant portions of datapath resources that remain unnecessarily activated in the course of program execution. We present a simple scheme for selectively activating regions within the register file and the reorder buffer for reducing leakage as well as dynamic power dissipation. Our techniques result in power savings in excess of 60% in these components, on the average with no performance loss.