MOVE: a framework for high-performance processor design
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
The energy complexity of register files
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Microprocessor Architectures: From VLIW to Tta
Microprocessor Architectures: From VLIW to Tta
Introduction to Algorithms
A cycle-accurate compilation algorithm for custom pipelined datapaths
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
An Energy-Efficient Processor Architecture for Embedded Systems
IEEE Computer Architecture Letters
Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Operand Registers and Explicit Operand Forwarding
IEEE Computer Architecture Letters
Customized Exposed Datapath Soft-Core Design Flow with Compiler Support
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Low-power, high-performance TTA processor for 1024-point fast fourier transform
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
ACM Transactions on Architecture and Code Optimization (TACO)
Transport triggered architecture to perform carrier synchronization for LTE
ACM Transactions on Embedded Computing Systems (TECS)
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In modern processor architectures, the register file (RF) consumes considerable amount of the processor power. It is well known that by allowing software to have explicit fine-grained control over the datapath, the transport-triggered architectures (TTAs) can substantially reduce the RF traffic, thereby minimizing the RF energy. However, it is important to make sure that the gain in RF is not cancelled out by the overhead due to the fine-grained datapath control, in particular, the deterioration of code density in conventional TTAs. In this paper, we analyze the potential of minimizing RF energy in MOVE-Pro, a TTA-based processor framework. We present a flexible compiler backend, which performs energy-aware instruction scheduling to push the limit of RF energy reduction. The experimental results show that with the proposed energy-aware compiler backend, MOVE-Pro is able to significantly reduce RF energy compared to its RISC/VLIW counterparts, by up to 80%. Meanwhile the code density of MOVE-Pro remains at the same level as its RISC/VLIW counterparts, allowing the energy saving in RF to be successfully transferred to total energy saving.