Low-power, high-performance TTA processor for 1024-point fast fourier transform

Authors:
Teemu Pitkänen;Risto Mäkinen;Jari Heikkinen;Tero Partanen;Jarmo Takala
Affiliations:
Tampere University of Technology, Tampere, Finland;Tampere University of Technology, Tampere, Finland;Tampere University of Technology, Tampere, Finland;Tampere University of Technology, Tampere, Finland;Tampere University of Technology, Tampere, Finland
Venue:
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Year:
2006

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Abstract

Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complex-valued fast Fourier transform (FFT). The proposed processor consumes only 1.55 μJ of energy for a 1024-point FFT. Compared to other reported FFT implementations with reasonable performance, the proposed design shows a significant improvement in energy-efficiency.