Low-power twiddle factor unit for FFT computation

Authors:
Teemu Pitkänen;Tero Partanen;Jarmo Takala
Affiliations:
Tampere University of Technology, Tampere, Finland;Tampere University of Technology, Tampere, Finland;Tampere University of Technology, Tampere, Finland
Venue:
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Year:
2007

Citing 2
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SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
A hardware efficient control of memory addressing forhigh-performance FFT processors

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Low-Power Application-Specific Processor for FFT Computations

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Abstract

An integral part of FFT computation are the twiddle factors, which, in software implementations, are typically stored into RAM memory implying large memory footprint and power consumption. In this paper, we propose a novel twiddle factor generator based on reduced ROM tables. The unit supports both radix-4 and mixed-radix-4/2 FFT algorithms and several transform lengths. The unit operates at a rate of one factor per clock cycle.