Design Methodology for Offloading Software Executions to FPGA
Journal of Signal Processing Systems
Scheduling for register file energy minimization in explicit datapath architectures
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Orcc: multimedia development made easy
Proceedings of the 21st ACM international conference on Multimedia
Teaching system-on-chip design with FPGAs
Proceedings of the 10th FPGAworld Conference
Towards Generic Embedded Multiprocessing for RVC-CAL Dataflow Programs
Journal of Signal Processing Systems
Design of a transport triggered vector processor for turbo decoding
Analog Integrated Circuits and Signal Processing
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A popular way to exploit high level programming languages in FPGA designs is to use a soft-core with accompanying software development tools. However, a common shortcoming with the current soft-core offerings is their limited software execution capability: the required performance for the implementation can be often reached only with instruction set extensions. In this paper, we propose and evaluate an application-specific processor design toolset that uses a multi-issue exposed data path processor architecture template. The main benefit of the architecture is scalability with respect to instruction-level parallelism (ILP). The design flow allows the designer to freely customize the data path resources in the core to exploit the ILP available in computation intensive kernels. The design toolset includes a retargetable C compiler and an architecture simulator, making design space exploration feasible. The experiments show that a relatively small soft-core tailored with the toolset provides significant speedups on software execution without using any instruction set extensions. The best measured speedup in comparison to the major commercial soft-cores was fourfold in applications from the CHStone benchmark suite, while the amount of consumed FPGA resources remained moderate.