Clock period constrained minimal buffer insertion in clock trees

Authors:
Gustavo E. Téllez;Majid Sarrafzadeh
Affiliations:
Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL;Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL
Venue:
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Year:
1994

Citing 0
Cited 4

Clock distribution using multiple voltages

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Low-power clock distribution using multiple voltages and reduced swings

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion

EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Probabilistic Approach to Buffer Insertion

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper we investigate the problem of computing a lower bound on the number of buffers required when given a maximum clock frequency and a predefined clock tree. Using generalized properties of published CMOS timing models, we formulate a novel non-linear and a simplified linear buffer insertion problem. We solve the latter optimally with an O(n) algorithm. The basic formulation and algorithm are extended to include a skew upper bound constraint. Using these algorithms we propose further algorithmic extensions that allow area and phase delay tradeoffs. Our results are verified using SPICE3e2 simulations with MCNC MOSIS 2.0&mgr; models and parameters. Experiments show our buffer insertion algorithms can be used effectively for high-speed clock designs.