IEEE Transactions on Computers
Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Buffer insertion and sizing under process variations for low power clock distribution
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Low-power clock distribution using multiple voltages and reduced swings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Legitimate Skew Clock Routing with Buffer Insertion
Journal of VLSI Signal Processing Systems
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Clock tree optimization for electromagnetic compatibility (EMC)
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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