IEEE Transactions on Computers
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Buffer insertion and sizing under process variations for low power clock distribution
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Clock distribution design and verification for PowerPC microprocessors
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Bounded-skew clock and Steiner routing under Elmore delay
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Useful-skew clock routing with gate sizing for low power design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Clock-tree routing realizing a clock-schedule for semi-synchronous circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Minimizing wirelength in zero and bounded skew clock trees
Proceedings of the tenth annual ACM-SIAM symposium on Discrete algorithms
Clustering based fast clock scheduling for light clock-tree
Proceedings of the conference on Design, automation and test in Europe
UST/DME: a clock tree router for general skew constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
UST/DME: a clock tree router for general skew constraints
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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Due to process, manufacturing and system operating conditions in a real environment, clock jitter is inevitable. In the presence of jitter, zero or near-zero skew are not really safe for reliable clock operations. Appropriate skew or useful skew can serve as a safety margin to guard against clock jitter. In two-phase clocking, the nonoverlapping interval of two-phase clocks provides an additional degree of freedom to improve either the clock tree cost or jitter-tolerance. We construct a two-phase jitter-tolerant useful-skew tree (JT-UST) such that the susceptibility to clock jitter and the clock tree cost is minimized. Following the Deferred-Merge Embedding (DME) framework, we use a simulated annealing approach to explore the routing topologies and embeddings. Experimental results have shown 63% to 100% reduction of jitter-prone sink pairs over previous clock routing methods while having very comparable clock tree costs.