REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Jitter-tolerant clock routing in two-phase synchronous systems
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
The Synthesis Approach to Digital System Design
The Synthesis Approach to Digital System Design
Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Timing analysis considering temporal supply voltage fluctuation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Safe clocking for the setup and hold timing constraints in datapath synthesis
Proceedings of the 19th ACM Great Lakes symposium on VLSI
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As the feature size of VLSI becomes smaller, delay variations become a serious problem in VLSI. In this paper, we propose a novel class of robustness for a datapath against delay variations, which is named structural robustness against delay variation (SRV), and propose sufficient conditions for a datapath to have SRV. A resultant circuit designed under these conditions has a larger timing margin to delay variations than previous designs without sacrificing effective computation time. In addition, under any degree of delay variations, we can always find an available clock frequency for a datapath having SRV property to operate correctly, which could be a preferable characteristic in IP-based design.