Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Timing variation-aware high-level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Post-Silicon Clock-Timing Tuning Based on Statistical Estimation
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths
Proceedings of the 20th symposium on Great lakes symposium on VLSI
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The setup and hold timing constraints are two types of timing constraints, which should be kept by each operation, and they may be violated by the timing variation of control signals. In this paper, we show that we can solve such potential timing violations in high-level synthesis without degrading speed performance, but by devising register assignment and clocking scheme. That is, we will combine Backward-Data-Direction (BDD) clocking, Forward-Data-Direction (FDD) clocking, and Structural Robustness against delay Variation (SRV)-based register assignment to solve potential timing violations. First, we formulate the problem as a minimum register assignment problem for datapaths which has a proper ordered clocking. After that, we propose an integer linear programming (ILP) formulation and show the experimental results for some benchmark circuits.