The Synthesis Approach to Digital System Design
The Synthesis Approach to Digital System Design
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A variation aware high level synthesis framework
Proceedings of the conference on Design, automation and test in Europe
Safe clocking for the setup and hold timing constraints in datapath synthesis
Proceedings of the 19th ACM Great Lakes symposium on VLSI
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Considering the timing uncertainty/variation of control signals and a clock signal to components, this paper proposes a novel resource sharing model which overcomes the risks of malfunctions caused by the timing problems. control timings, and proposes resource sharing conditions to FU assignment, which guarantee correct timings of control signals to multiplexers and registers under delay uncertainty/variation. This approach is combined with ``ordered clocking'' which is another mechanism to guarantee the correct timing, and the final resource sharing model is devised. There is a major drawback: the increase in latency. As the first step, the latency minimization problem under the proposed resource sharing model is formulated, and a simple List Scheduling-based algorithm is proposed as a solution algorithm. The proposed method is evaluated by experimental results for some benchmark circuits.