Post-Silicon Clock-Timing Tuning Based on Statistical Estimation

Authors:
Yuko Hashizume;Yasuhiro Takashima;Yuichi Nakamura
Affiliations:
-;-;-
Venue:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Year:
2008

Citing 4
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Abstract

In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. As a countermeasure to the variations, post-silicon tuning has been proposed. Deskew, where the clock timing of flip-flops (FFs) is tuned by inserted programmable delay elements (PDEs) into the clock tree, is classified into this method. We propose a novel deskew method that decides the delay values of the elements by measuring a small amount of FFs' clock timing and presuming the rest of FFs' clock timings based on a statistical model. In addition, our proposed method can determine the discrete PDE delay value because the rewriting constraint satisfies the condition of total unimodularity.