Statistical Analysis of Clock Skew Variation in H-Tree Structure

Authors:
Masanori Hashimoto;Tomonori Yamamoto;Hidetoshi Onodera
Affiliations:
The authors are with Department of Communications and Computer Engineering, Kyoto University, Kyoto-shi, 606-8501 Japan. E-mail: hasimoto@ist.osaka-u.ac.jp,;The authors are with Department of Communications and Computer Engineering, Kyoto University, Kyoto-shi, 606-8501 Japan. E-mail: hasimoto@ist.osaka-u.ac.jp,;The authors are with Department of Communications and Computer Engineering, Kyoto University, Kyoto-shi, 606-8501 Japan. E-mail: hasimoto@ist.osaka-u.ac.jp,
Venue:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Year:
2005

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Abstract

This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important design parameter that controls clock skew and power dissipation. In this paper, we evaluate clock skew under several variability models, and demonstrate relationship among clock skew, transition time constraint and power dissipation. Experimental results show that constraint of small transition time reduces clock skew under manufacturing and supply voltage variabilities, whereas there is an optimum constraint value for temperature gradient. Our experiments in a 0.18 μm technology indicate that clock skew is minimized when clock buffer is sized such that the ratio of output and input capacitance is four.