Statistical Analysis of Clock Skew Variation in H-Tree Structure
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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We present on-chip oscillator arrays synchronized by random noises, aiming at skew-free clock distribution on synchronous digital systems. Nakao et al. recently reported that independent neural oscillators can be synchronized by applying temporal random impulses to the oscillators [1],[2]. We regard neural oscillators as independent clock sources on LSIs; i.e., clock sources are distributed on LSIs, and they are forced to synchronize through the use of random noises. We designed neuron-based clock generators operating at sub-RF region (