An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits

Authors:
Akira Utagawa;Tetsuya Asai;Tetsuya Hirose;Yoshihito Amemiya
Affiliations:
-;-;-;-
Venue:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Year:
2007

Citing 6
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Abstract

We designed subthreshold analog MOS circuits implementing an inhibitory network model that performs noise-shaping pulse-density modulation (PDM) with noisy neural elements, with the aim of developing a possible ultralow-power one-bit analog-to-digital converter. The static and dynamic noises given to the proposed circuits were obtained from device mismatches of current sources (transistors) and externally applied random spike currents, respectively. Through circuit simulations we confirmed that the circuit exhibited noise-shaping properties, and signal-to-noise ratio (SNR) of the network was improved by 7.9 dB compared with that of the uncoupled network as a result of noise shaping.