Introduction to algorithms
IEEE Transactions on Computers
On the temporal equivalence of sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Reliable non-zero skew clock trees using wire width optimization
DAC '93 Proceedings of the 30th international Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Concurrent timing optimization of latch-based digital systems
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Clocking optimization and distribution in digital systems with scheduled skews
Clocking optimization and distribution in digital systems with scheduled skews
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System performance can be improved by employing scheduled skews atflip-flops. This optimization technique is called skewed-clockoptimization and has been successfully used in memory designs toachieve high operating frequencies. There are two important issues indeveloping this optimization technique. The first is the selection ofappropriate clock skews to improve system performance. The second isto reliably distribute skewed clocks in the presence of manufacturingand environmental variations. Without the careful selection ofclocking times and control of unintentional clock skews, potentialsystem performance might not be achieved. In this paper atheoretical framework is first presented for solving the problem ofoptimally scheduling skews. A novel self-calibrating clockdistribution scheme is then developed which can automatically trackvariations and minimize unintentional skews. Clocks with properskews can be reliably delivered by such a scheme.