Shedding physical synthesis area bloat

Authors:
Ying Zhou;Charles J. Alpert;Zhuo Li;Cliff Sze;Louise H. Trevillyan
Affiliations:
IBM Austin Research Laboratory, Austin, TX;IBM Austin Research Laboratory, Austin, TX;IBM Austin Research Laboratory, Austin, TX;IBM Austin Research Laboratory, Austin, TX;IBM Waston Research Laboratory, Yorktown Heights, NY
Venue:
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Year:
2011

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Abstract

Area bloat in physical synthesis not only increases power dissipation, but also creates congestion problems, forces designers to enlarge the die area, rerun the whole design flow, and postpone the design deadline. As a result, it is vital for physical synthesis tools to achieve timing closure and low power consumption with intelligent area control. The major sources of area increase in a typical physical synthesis flow are from buffer insertion and gate sizing, both of which have been discussed extensively in the last two decades, where the main focus is individual optimized algorithm. However, building a practical physical synthesis flow with buffering and gate sizing to achieve the best timing/area/runtime is rarely discussed in any previous literatures. In this paper, we present two simple yet efficient buffering and gate sizing techniques and achieve a physical synthesis flow with much smaller area bloat. Compared to a traditional timing-driven flow, our work achieves 12% logic area growth reduction, 5.8% total area reduction, 10.1% wirelength reduction, and 770 ps worst slack improvement on average on 20 industrial designs in 65nm and 45 nm.