Variability driven gate sizing for binning yield optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we approach the gate sizing problem in VLSI circuits considering the variability of process parameters in the nano technology. We follow a penalty based approach in which violation of the timing/leakage constraints is associated with a penalty proportional to the degree of violation. We show that minimization of the expected value of this penalty can be optimally achieved due to inherent convexity of the expected penalty function without making any assumptions on the nature of variability and correlations. Such an approach is ideal in situations where the chips violating the timing and leakage constraints are sold at a loss (and not simply discarded). Comparision with state of the art sensitivity based approach demonstrate an improvement of 73.1% in the expected penalty/loss (also called cumulative yield loss) with an area overhead of 1.8%. Our approach also shows a speed-up of 2.41 times. We also show that minimization of the cumulative yield loss also improves the traditional yield loss of the circuit with a 68.86% improvement from a sensitivity based approach.