Variability driven gate sizing for binning yield optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a method to transistor sizing integrated to a row-based automatic layout generation tool. Automatic layout generation is able to generate more optimized layout in relation to the standard cell approach because standard cell libraries present limited number ofcells. Most of transistor sizing algorithms propose continuous sizing according to the performance constraints and hence cannot be applied in row-based layouts. In this paper,transistors are folded to keep the row height, sizing discretely the transistor. In order to save the final area of the circuit, only transistors in the longest sensitizable paths are sized. The efficiency of the algorithm is measured in relation to area and delay.