Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
A methodology to improve timing yield in the presence of process variations
Proceedings of the 41st annual Design Automation Conference
Novel sizing algorithm for yield improvement under process variation in nanometer technology
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis using Levelized Covariance Propagation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
A framework for statistical timing analysis using non-linear delay and slew models
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Guaranteeing performance yield in high-level synthesis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Non-linear statistical static timing analysis for non-Gaussian variation sources
Proceedings of the 44th annual Design Automation Conference
Variability-driven module selection with joint design time optimization and post-silicon tuning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Exact and approximate algorithms for the extension of embedded processor instruction sets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast Identification of Custom Instructions for Extensible Processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Profit maximization through process variation aware high level synthesis with speed binning
Proceedings of the Conference on Design, Automation and Test in Europe
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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The timing closure problem (e.g., meeting timing/ clock period constraint) is one of the most important problems in the design automation. However, the rapid increase of the impact of the process variation on circuit timing makes the problem much more complicated and unpredictable to tackle in synthesis. This paper addresses a new problem of high-level synthesis (HLS) that effectively takes into account the timing variation. Conventional HLS may simply avoid the timing variation problem by considering the worst case or constant delay model of hardware resources, which are certainly not viable solutions. To overcome the impact of timing variation in HLS, this paper addresses the following two problems: 1) how can the statistical static timing analysis (SSTA) used in logic synthesis be modified and effectively applied to the delay and yield computation in HLS? and 2) how can scheduling and resource binding tasks effectively solve the HLS problem with the objective of minimizing latency under yield constraint? Through an extensive experimentation, we confirm that the proposed variation-aware HLS algorithm is able to reduce the latency by 19.7% under 90% performance yield constraint, compared with the result by conventional timing variation-unaware HLS [16].