Complexity-effective superscalar processors
Proceedings of the 24th annual international symposium on Computer architecture
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Closed-loop adaptive voltage scaling controller for standard-cell ASICs
Proceedings of the 2002 international symposium on Low power electronics and design
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Microarchitecture parameter selection to optimize system performance under process variation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking
PACT '07 Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques
Circuit techniques for dynamic variation tolerance
Proceedings of the 46th Annual Design Automation Conference
Selective wordline voltage boosting for caches to manage yield under process variations
Proceedings of the 46th Annual Design Automation Conference
Overscaling-friendly timing speculation architectures
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Recovery-driven design: a power minimization methodology for error-tolerant processor modules
Proceedings of the 47th Design Automation Conference
Scalable stochastic processors
Proceedings of the Conference on Design, Automation and Test in Europe
Slack redistribution for graceful degradation under voltage overscaling
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Stochastic computing: embracing errors in architectureand design of processors and applications
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
On software design for stochastic processors
Proceedings of the 49th Annual Design Automation Conference
Compiling for energy efficiency on timing speculative processors
Proceedings of the 49th Annual Design Automation Conference
RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors
Proceedings of the 50th Annual Design Automation Conference
Post-placement voltage island generation for timing-speculative circuits
Proceedings of the 50th Annual Design Automation Conference
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Escalating variations in modern CMOS designs have become a threat to Moore's law. While previous works have proposed techniques for tolerating variations by trading reliability for reduced voltage (energy) [10], the benefits of such techniques are limited, because voltage/reliability tradeoffs in conventional processors often introduce more errors than can be gainfully tolerated [14]. Recent work has proposed circuit and design-level optimizations [14, 15]that manipulate the error rate behavior of a design to increase the potential for energy savings from voltage/reliability tradeoffs. In this paper, we investigate whether architectural optimizations can also manipulate error rate behavior to significantly increase the energy savings from voltage/reliability tradeoffs. To this end, we demonstrate how error rate behavior indeed depends on processor architecture, and that architectural optimizations can be used to manipulate the error rate behavior of a processor. We show that architectural optimizations can significantly enhance voltage/reliability tradeoffs, achieving up to 29% additional energy savings for processors that employ Razor-based error resilience.