The fanout problem: from theory to practice
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Performance-oriented technology mapping
Performance-oriented technology mapping
LATTIS: an iterative speedup heuristic for mapped logic
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Performance optimization of digital circuits
Performance optimization of digital circuits
A methodology and algorithms for post-placement delay optimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
New algorithms for gate sizing: a comparative study
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
A fast fanout optimization algorithm for near-continuous buffer libraries
DAC '98 Proceedings of the 35th annual Design Automation Conference
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Bounding Fan-out in Logical Networks
Journal of the ACM (JACM)
LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An integrated placement and synthesis approach for timing closure of PowerPC/sup TM/ microprocessors
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
A Robust Solution to the Timing Convergence Problem in High-Performance Design
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Gate sizing in MOS digital circuits with linear programming
EURO-DAC '90 Proceedings of the conference on European design automation
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We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. The contribution of our work lies in the integration of the three techniques, allowing them to interact at a much finer level of granularity than would be otherwise possible. This produces better results than those obtainable by individual techniques like net buffering or gate resizing applied to the circuit in various combinations. GDM transform is also layout-friendly since it does not alter the routing patterns and placement of cells, except possibly some buffer insertions/deletions. Hence it is useful for achieving timing closure in late stages of the design flow. We propose a comprehensive GDM algorithm that (a) determines the best replacement of a gate, possibly with inverted inputs and outputs, along with the best buffering configurations of nets incident on it, and (b) embeds this into a global scheme for optimizing large designs. We have implemented this algorithm in a layout-driven, industrial-strength logic optimization framework, and have successfully applied it to large industrial designs.